A complete Information Security Management System implementation built specifically around the risk profile of a design engineering environment, including pre-silicon IP protection, EDA vendor governance, and design data handling. The engagement is structured around semiconductor engineering requirements rather than a generic enterprise security template.
Semiconductor design environments have specific information security considerations involving pre-silicon intellectual property, engineering data, EDA vendors, design access, and controlled information flows. An ISMS implementation needs to address these engineering risks as part of the certification journey.
- Phase 0: Gap assessment and roadmap, weeks 1 to 4
- Phase 1: Foundation documents, weeks 5 to 12
- Phase 2: Risk assessment and SoA, weeks 13 to 26
- Phase 3: Operationalise and train, weeks 27 to 40
- Phase 4: Certification readiness, weeks 41 to 52
- Stage 1 and Stage 2 audit support
- Gap assessment report against all 93 controls
- Complete ISMS documentation set, 19 documents
- Risk register and Statement of Applicability
- Internal audit programme and audit delivery
- Security awareness training programme
- Certification body liaison and audit support
Available as a standalone Gap Assessment (₹1,25,000 to ₹2,00,000, 3 to 4 weeks) if you want to establish the baseline before committing to full implementation.
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Let's discuss your ISMS requirements, certification objectives, semiconductor security risks, and implementation roadmap.
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